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Chapter 8 Real-Time System Integration Bus (RTSI)
E Series User Manual 8-4 ni.com
Device and RTSI Clocks
Many E Series device functions require a frequency timebase to generate
the necessary timing signals for controlling A/D conversions, DAC
updates, or general-purpose signals at the I/O connector. This timebase is
also called the Master Timebase or Onboard Clock. Refer to the Master
Timebase Signal section of Chapter 5, Counters, for more information.
Most E Series devices can use either their internal 20 MHz or 100 kHz
timebase or a timebase received over the RTSI bus. The timebase can only
be routed to or received from RTSI 7, or the RTSI clock. The device
directly uses this clock source, whether local or from the RTSI bus, as the
primary frequency source. If you configure the device to use the internal
timebase, you also can program the device to drive its internal timebase
over the RTSI bus to another device that is programmed to receive this
timebase signal. The default configuration at startup is to use the internal
timebase without driving the RTSI bus timebase signal.
Note DAQCard and DAQPad devices do not interface to the RTSI bus.
Synchronizing Multiple Devices
With the RTSI bus and the routing capabilities of the DAQ-STC, there are
several ways to synchronize multiple devices depending on your
application. NI recommends that you use a common timebase as the
MasterTimebase signal and share any common triggers in the application.
One device is designated as the master device and all other devices are
designated as slave devices.
The 20MHzTimebase on the master device is the MasterTimebase signal
for all devices. The slave devices pull this signal from the master device
across the RTSI Trigger 7 line. Slave devices also pull any shared triggers
across an available RTSI trigger line from the master device. When you
start all of the slave devices before starting the master device, you have
successfully synchronized your application across multiple devices.
For more information, refer to Synchronizing E Series Devices in the
NI-DAQmx Help or the LabVIEW 8.x Help.
- DAQ E Series 1
- Important Information 3
- Compliance 4
- Chapter 2 6
- Chapter 3 8
- Contents 10
- About This Manual 12
- Related Documentation 13
- NI-DAQmx Base 14
- LabWindows/CVI 15
- Measurement Studio 15
- Training Courses 17
- Technical Support on the Web 17
- DAQ System Overview 18
- DAQ Hardware 19
- Calibration Circuitry 20
- Signal Conditioning 21
- Signal Conditioning Options 22
- Cables and Accessories 23
- Chapter 1 DAQ System Overview 24
- Custom Cabling 26
- Terminal Name Equivalents 31
- +5 V Power Source 33
- Input Polarity and Range 35
- Chapter 2 Analog Input 38
- Figure 2-2. E Series PGIA 39
- Table 2-5. NI-PGIA Signal 40
- Figure 2-3. Dither 42
- Use Low Impedance Sources 43
- Example 1 45
- Example 2 46
- AI Data Acquisition Methods 46
- Software-Timed Acquisitions 46
- Hardware-Timed Acquisitions 46
- Analog Input Triggering 47
- AI Start Trigger Signal 48
- Using a Digital Source 48
- Using an Analog Source 48
- = 50 to 100 ns 49
- Pre-Trigger Samples 50
- Reference Trigger 50
- Post-Trigger Samples 50
- Complete Buffer 50
- Types of Signal Sources 55
- Floating Signal Sources 55
- (RSE Configuration) 60
- (NRSE Configuration) 60
- Field Wiring Considerations 61
- Traditional NI-DAQ (Legacy) 62
- NI-DAQmx 62
- Analog Input Timing Signals 63
- Figure 2-16. Interval Sample 64
- AI Sample Clock Signal 70
- Using an Internal Source 70
- Using an External Source 70
- Other Timing Requirements 72
- AI Convert Clock Signal 74
- AI Hold Complete Event Signal 79
- External Strobe Signal 79
- Reference Selection 82
- Polarity Selection 83
- Reglitch Selection 83
- AO Data Generation Methods 84
- Analog Output Triggering 85
- AO Start Trigger Signal 86
- = 25 to 50 ns 87
- Chapter 3 Analog Output 88
- AO Sample Clock Signal 91
- = 50 to 75 ns 92
- Digital I/O 96
- Extended Digital I/O 97
- Power-On State 98
- Timing Specifications 99
- Chapter 4 Digital I/O 100
- Mode 1 Input Timing 101
- Mode 1 Output Timing 102
- Mode 2 Bidirectional Timing 103
- Configured for Digital Output 105
- Counters 106
- Counter Timing Signals 107
- Counter 0 Source Signal 108
- Counter 0 Gate Signal 109
- Chapter 5 Counters 110
- CTR 0 OUT Pin 111
- Counter 0 Up/Down Signal 111
- Counter 1 Source Signal 111
- Counter 1 Gate Signal 112
- Counter 1 Up/Down Signal 114
- Frequency Output Signal 114
- Master Timebase Signal 114
- Programmable Function 116
- Interfaces (PFI) 116
- Digital Routing 118
- Chapter 7 Digital Routing 119
- Connecting Timing Signals 121
- Routing Signals in Software 122
- Real-Time System Integration 123
- Bus (RTSI) 123
- PXI E Series Devices 124
- Device and RTSI Clocks 126
- Bus Interface 127
- Data Transfer Methods 128
- Chapter 9 Bus Interface 129
- Triggering 130
- Chapter 10 Triggering 131
- PFI 0/AI START TRIG Pin 132
- Analog Input Channel 132
- Analog Trigger Actions 132
- Analog Trigger Types 133
- Window Triggering 134
- Analog Trigger Accuracy 135
- Device-Specific Information 136
- I/O Connector 137
- NI 6013/6014 Family 140
- NI 6013/6014 Block Diagram 141
- NI 6013/6014 Specifications 141
- NI 6013 Pinout 141
- Figure A-4. NI 6013 Pinout 142
- NI 6014 Pinout 143
- Figure A-5. NI 6014 Pinout 144
- NI 6015/6016 Family 145
- NATIONAL 146
- INSTRUMENTS 146
- DAQ - STC 147
- USB ConnectorExternal Power 147
- I/O Connectors 147
- Analog Input 148
- Single-Ended Signals 149
- Analog Output 150
- User <1..2> 151
- Other Signals 152
- DAQPad-6015/6016 LED Patterns 153
- NI DAQPad-6015 Pinout 156
- NI DAQPad-6015 BNC Pinout 157
- NC = No Connect 158
- NI 6020E Family 159
- DAQPad-6020E Block Diagram 161
- AO External Reference 164
- DAQPad-6020E LED Patterns 167
- DAQPad-6020E Specifications 167
- NI DAQPad-6020E Pinout 167
- NI DAQPad-6020E BNC Pinout 169
- NI 6023E/6024E/6025E Family 170
- NI 6023E Pinout 172
- Figure A-37. NI 6023E Pinout 173
- NI 6024E Pinout 174
- Figure A-38. NI 6024E Pinout 175
- NI 6025E Pinout 176
- PCI/PXI Bus 179
- NI 6030E Pinout 180
- Figure A-42. NI 6030E Pinout 181
- NI 6031E Pinout 184
- Figure A-44. NI 6031E Pinout 185
- NI 6032E Pinout 186
- Figure A-45. NI 6032E Pinout 187
- NI 6033E Pinout 188
- Figure A-46. NI 6033E Pinout 189
- NI 6034E/6035E/6036E Family 190
- NI 6034E Pinout 192
- Figure A-49. NI 6034E Pinout 193
- NI 6035E Pinout 194
- Figure A-50. NI 6035E Pinout 195
- NI 6036E Pinout 196
- Figure A-51. NI 6036E Pinout 197
- NI 6040E Family 198
- NI 6040E Pinout 199
- Figure A-53. NI 6040E Pinout 200
- PCI-MIO-16E-4 201
- PCI-MIO-16E-4 Block Diagram 202
- NI 6052E Family 204
- DAQPad-6052E Block Diagram 206
- DAQPad-6052E LED Patterns 212
- NI DAQPad-6052E Pinout 212
- NI DAQPad-6052E BNC Pinout 214
- NI PCI/PXI-6052E 214
- NI PCI/PXI-6052E Pinout 215
- NI DAQCard-6062E 217
- DAQCard-6062E Block Diagram 218
- DAQCard-6062E Specifications 218
- NI DAQCard-6062E Pinout 218
- Figure A-72. NI 6062E Pinout 219
- NI 6070E/6071E Family 220
- DAQPad-6070E Block Diagram 222
- Figure A-83 227
- DAQPad-6070E LED Patterns 228
- NI DAQPad-6070E BNC Pinout 228
- NI 6070E/6071E Block Diagram 230
- NI PCI/PXI-6070E Pinout 230
- NI PCI-6071E Pinout 232
- PCI-MIO-16E-1 234
- PCI-MIO-16E-1 Block Diagram 235
- NI 6070E/6071E Specifications 237
- I/O Connector Pinouts 238
- 100-68-68-Pin 240
- NC = No connect 241
- 100-50-50-Pin 243
- 50-pin connectors 244
- Troubleshooting 246
- Channel 0 247
- Channel 1 247
- Convert Period 247
- Sample Period 247
- Appendix C Troubleshooting 248
- Technical Support and 249
- Professional Services 249
- Glossary 251
- Numerics 258
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